1. Field of the Invention
The present invention relates to a method for manufacturing a multilayer wiring board used in the circuitry of electrical and electronic devices.
2. Description of the Related Art
As demand has increased in recent years for electronic devices that are smaller, offer higher performance, and are less expensive, the high-density mounting of the electronic parts incorporated in these electronic devices has been increasingly rapidly. To meet this need for high-density mounting, a built-up multilayer wiring structure in which multiple layers of wiring are formed is sometimes employed for the substrate on which the electronic parts are mounted. With a built-up multilayer wiring structure, wiring patterns are embedded between a plurality of built-up insulating layers, and the various wiring patterns are electrically connected by vias provided to via holes made in the insulating layers.
To form a built-up multilayer wiring structure, first a built-up insulating layer is formed on a supporting substrate or another built-up insulating layer on which a wiring pattern has already been formed, from above this wiring pattern. Next, a via hole is formed in this insulating layer. Methods that have been employed to form via holes include forming a hole in the insulating layer by photolithography using a photosensitive resin as the insulating layer material, and a method in which a hole is formed in the insulating layer by irradiation with a laser.
After the via hole has been formed in the insulating layer, a film of a conductor material is formed over the insulating layer by electroless plating or electroplating. The conductor material here forms a via in the via hole. Next, a wiring pattern is formed by etching the conductor material film. After a wiring pattern has thus been formed on the insulating layer, the series of steps from the lamination of the insulating layer up to the wiring pattern formation is repeated as many times as necessary, which allows a multilayer circuit to be produced, and as a result the degree of integration of the circuit can be raised.
With a conventional multilayer wiring board having a built-up multilayer wiring structure such as this, the wiring pattern is formed over the insulating layer only after the surface of the insulating layer has been subjected to a roughening treatment in order to ensure good adhesion between the insulating layer and the wiring pattern. More specifically, bumps and recesses are formed at an Rmax of about 5 μm, for example, on the exposed insulating layer surface, over which first electroless copper plating and then copper electroplating are performed, thereby forming a copper wiring pattern. This roughening of the insulating layer surface affords good adhesion through a physical anchoring effect between the insulating layer and the copper wiring pattern.
Nevertheless, with this conventional process, it was still sometimes impossible to achieve the desired adhesion between the insulating layer and the wiring pattern. For instance, the peel strength, as given by the 90-degree peel test set forth in JIS C 6481, is usually less than 1 kgf/cm. If the adhesion is insufficient between the insulating layer and the wiring pattern, there will tend to be such problems as the inability to form a good micro-wiring structure.
Also, if the insulating layer surface is roughened to a surface roughness (Rmax) of about 5 μm, then with wiring having a small contact area with the insulating layer, the adhesion to the insulating layer will tend to decrease, which may preclude a reduction in wiring size. Consequently, the adhesion of a wiring pattern to an insulating layer in a built-up wiring structure must be good enough that a peel strength of at least 1 kgf/cm can be achieved in the above-mentioned 90-degree peel test, while the insulating layer is only roughened to an extent that will not hamper a reduction in wiring size.